This invention relates to a logic synthesis system for synthesizing a design of a logic circuit from a system input signal with reference to a translation table.
For the logic synthesis system of the type described, the system input signal represents an input logical expression of the logic circuit. The logic synthesis system thereby produces a system output signal representative of the design.
A conventional logic synthesis system comprises a memory for memorizing a plurality of fundamental code signals as memorized code signals and a plurality of fundamental pattern signals as memorized pattern signals in the form of a translation table. The fundamental code signals represent fundamental codes, respectively. The fundamental pattern signals represent fundamental patterns, respectively. The fundamental patterns are in one-to-one correspondence to the fundamental codes. The memory therefore memorizes translation rules indicative of the fundamental codes and the corresponding fundamental patterns in pairs.
Responsive to the system input signal, an intermediate code producing circuit produces an intermediate code signal representative of an intermediate code. The intermediate code corresponds to the input logical expression.
Connected to the memory and the intermediate code producing circuit, a translating circuit translates, with reference to the translation table, the intermediate code signal into a translated signal. The translating circuit will now be described a little more in detail. Responsive to the intermediate code signal, the translating circuit locates, as a located code signal, one of the memorized code signals that matches with the intermediate code signal. Subsequently, the translating circuit produces, as the translated signal, one of the memorized pattern signals that corresponds to the located code signal. The translated signal is used as the system output signal.
Such a logic synthesis system is disclosed, for example, by Takeshi YOSHIMURA in a Japanese technical paper published Oct. 21, 1987, by "Densi Joohoo Tuusin Gakkai" (the Institute of Electronics, Information and Communication Engineers of Japan), VLD87-92, pages 9-16, under the title of "Ruuru Beesu to Arugorizumu ni motozuku Ronri Goosei Sisutemu (A Logic System Based on Rule-based and Algorithmic Approach)".
The conventional logic synthesis system is disadvantageous in that an increased number of the translation rules must be memorized in the memory in order to synthesize various designs of the logic circuits. Therefore, it is not easy to form the translation table in the memory. In addition, it is necessary to supply the system input signal to the logic synthesis system by the use of the memorized fundamental codes which are memorized in the memory. Thus, the system input signal is restricted by the fundamental codes.